1. Field of the Invention
The embodiments of the invention generally relate to selective voltage binning and, more particularly, an integrated circuit design timing closure method for selective voltage binning.
2. Description of the Related Art
Consumers continue to demand smaller electronic devices with ever small power requirements. Power consumption from the complementary metal oxide semiconductor (CMOS) integrated circuits commonly used to build such electronic devices consists of two components: dynamic (active) power consumption and static (leakage) power consumption. Dynamic power consumption refers to the amount of power required to operate (i.e., switch) a device. Dynamic power consumption is a function of capacitance, voltage, and switching frequency. That is P=CV2F, where P is the dynamic power, C is the effective switch capacitance, V is the supply voltage and F is the switching frequency. Static power consumption refers to the amount of power consumed by the device when it is not operating (i.e., OFF) and is also an exponential function of the supply voltage. In the past static power consumption was an insignificant portion of overall power consumption. However, with device scaling the ratio of static to dynamic power making up overall power consumption has increased. Thus, optimizing not only dynamic power consumption but also static power consumption is now a major concern for designers of advanced integrated circuits (ICs).
In addressing the issue of static power consumption, designers have realized that manufacturing variations are a critical problem. Specifically, manufacturing variations may cause one or more parameters to vary between integrated circuits that are formed according to the same design. These variations can affect chip operating frequency (i.e., switching speed). For example, due to variations in the equipment, operators, position on a wafer, etc., a specific parameter may vary between chips built on the same wafer, chips built on different wafers in the same lot and/or on chips built on different wafers in different lots. If this parameter is, for example, line width, then the channel width of the transistors on each chip may be different such that the performance varies (e.g., faster or slower). Chips that are fabricated either at the “slow” end or the “fast” end of a process distribution (e.g., a process-temperature-variation (PVT) space) may not be desirable. For example, chips that are fabricated at the “slow” end of such a process distribution may not meet the desired performance specification (i.e., may not have a fast enough switching speed), whereas chips fabricated at the “fast” end of this process distribution may exhibit excessive power and leakage current.
Pre-release chip “design closure” methodologies seek to guarantee circuit timing across the full process distribution for entire ranges of expected voltage and temperature conditions. However, as process control has become more and more difficult, timing closure over the full process distribution has become quite challenging.
Additionally, post-manufacturing voltage binning is a technique that is used to sort manufactured chips into bins based on whether they were fabricated at either the “slow” end or the “fast” end of a process distribution and to vary the voltage requirements for the chips depending upon the bins they are assigned to in order to reduce maximum chip power. Specifically, with slower process chips it takes more voltage to turn on a transistor and less current is produced to drive the load. Thus, in the past the worst case process ranges drove the required voltage for ultimately running the chip. However, with selective voltage binning, every chip is tested to measure operating speed and the chips are sorted accordingly. For example, in a process-voltage-temperature space, the temperature and voltage of the chip may be fixed and the switching frequency may be measured. If the switching frequency is high, then the chip is on the fast end of the process-voltage-temperature space and placed in a fast chip bin. If the switching frequency is low, then the chip is on the slow end of the process-voltage-temperature space and placed in a slow chip bin. After the chips are sorted into bins, an optimal supply voltage (Vdd) for operating the chips in each bin is determined. Since both dynamic power consumption and static power consumption are exponentially proportional to the Vdd, a reduction in the required Vdd will reduce both dynamic and leakage power consumption and, thus, overall power consumption. Therefore, a customer might, for example, be instructed that a fast chip from a fast chip bin may be operated at a certain reduced Vdd in order to minimize static power consumption, while still meeting a given performance specification (i.e., still operating at a desired speed). Whereas, a customer may be instructed that a slow chip from a slow chip bin should be operated at the maximum achievable Vdd in order to meet another performance specification.
It would be advantageous over the prior art to provide a method of designing and manufacturing a chip that combines the pre-release chip design timing closure process with the post-manufacturing binning processes in order to deliver chips that exhibit the best possible performance at acceptable levels of power. Therefore, disclosed herein is a method which subdivides the full process distribution into smaller timing closure intervals during pre-release chip design, each of which is independently optimized for performance versus power by assigning specific application power supply voltage ranges that correspond to each interval. Then, after chip manufacturing, the method tests the timing of each chip and sorts the chips into bins corresponding to the assigned power supply voltage ranges used in the timing closure process.